In integrated circuit art, a commonly used method for forming metal lines and vias is known as “damascene.” Generally, this method involves forming an opening in a dielectric layer, which separates the vertically spaced metallization layers. The opening is typically formed using conventional lithographic and etching techniques. After the formation, the opening is filled with copper or copper alloys. Excess copper on the surface of the dielectric layer is then removed by a chemical mechanical polish (CMP). The remaining copper or copper alloy forms vias and/or metal lines.
Copper is commonly used in the damascene structures because of its low resistivity. Typically, copper is electro plated into damascene openings. As is well known in the art, in order to plate copper, a seed layer is required to provide a low-resistance electrical path, and hence to enable uniform electro-plating over the wafer surface, so that copper ions in the plating solution can be deposited.
FIG. 1 illustrates a cross-sectional view of an intermediate stage in the formation of a conventional damascene structure. Trench opening 10 is formed in low-k dielectric layer 2, followed by the blanket formation of diffusion barrier layer 4. Next, copper seed layer 6 (including portions 61, 62, 63—1, and 63—2) is formed, either by physical vapor deposition (PVD), or by electroless plating. FIG. 1 illustrates a typical profile of seed layer 6 formed of PVD. Due to the fact that copper atoms are deposited downwardly, horizontal seed layer portions 61 and 62, which are over low-k dielectric layer 2 and in trench opening 10, respectively, are much thicker than portions 63—1 and 63—2 on sidewalls of trench opening 10. Furthermore, a necking effect often occurs, so that on the sidewalls of trench opening 10, top portions 63—1 of seed layer 6 are thicker than bottom portions 63—2, resulting in overhangs. The non-uniformity in the profile of seed layer 6 will adversely affect the quality of the subsequently performed electro plating.
Besides the adverse profile of seed layer 6 in the trench openings, asymmetry effects also result, and the asymmetry effects depend on the relative position of the trench opening on a wafer. For example, for a trench opening located close to an edge of a wafer, the side of the trench opening closer to the center of the wafer and the side closer to the edge of the wafer may have significantly different sidewall seed layer thicknesses. Also, overhangs of seed layers are more severe at the center portion of the wafer than at the edge portions. Further, the thickness of sidewall seed layer closer to the edge of the wafer is often less then those closer to the center of the wafer. All these asymmetry effects adversely affect the performance and reliability of the resulting interconnect structure.
One of the methods for reducing the above-discussed non-uniformity in a seed layer profile is to reduce the deposition rate of seed layer 6, for example, using very small power and/or adopting very low pressure in the process chamber. As a result, the throughput becomes very low, and hence this method is not suitable for mass production. New methods for improving the uniformity of seed layers without sacrificing the throughput are thus needed.